The present invention relates to an arrangement for handling redundant signals in the form of data from at least two planes wherein a buffering arrangement receives a number of unsynchronized data streams from a number of different planes with each a clock system wherein buffering means are provided for handling dynamic phase deviations between the planes and for handling static phase deviations between the planes.
The invention also relates to a method for handling redundant signals in the form of a number of unsynchronized data streams from a number of different planes in a buffering arrangement wherein dynamic phase deviations between the planes and static phase deviations between the planes are handled.
Still further the invention relates to a telecommunication system comprising an arrangement of the above mentioned kind.
In transmission systems or communication systems such as e.g. telecommunication systems the amount of information transmitted is often very high and protection is applied in different ways to reduce the risks of information being lost and to reduce the risk of faulty transmission of information.
Since in communication systems information or data is often transported as signals at high speeds and the signals often also carry large amounts of data it is of great importance that such signals can be protected in an efficient way. In telecommunication systems the signals may carry a high number of telephone calls, e.g. 2000 calls or similar and it is obvious that such signals must have a high availability.
In various known systems are e.g. switching matrixes or cross-connects multiplicated. In some known systems the switching matrixes are triplicated whereas in other systems they are duplicated.
Triplication is often applied because in that way fault isolation is facilitated since majority vote can be taken in the terminating unit as user of the signal. In the terminating unit the three incoming data streams are converted into one. Particularly if the system is a high speed system the triplication causes problems, namely that it is difficult to keep the planes synchronized since data arrive asynchronously from three different planes. Often it is also desirable to be able to use long cables. Therefore the phase relations between the clock systems of the planes are not known in the clock exchange buffers in the terminating unit. In a known system the buffering arrangement is divided into first buffering means for handling the dynamic phase deviations and second buffering means for compensating for static differences or delays resulting from different cable lengths. If one of the planes is faulty or for some reason has to be taken down, the write pointer of the dynamic buffer for e.g. the master plane is copied to the dynamic buffer of a slave plane, i.e. here the plane that was taken down, to be able to restart the slave plane. However, there is a one clock cycle uncertainty when the dynamic buffer reloads one of its internal write pointers from a selected master which means that the delay through the dynamic buffer can change when a reload operation is performed. This delay is compensated for in the static buffer and for a number of consecutive reload operations, the static buffer may be forced to one of its end positions which means that the triplicated system may have to be taken down due to end of buffer for all three planes which is clearly disadvantageous.
In today known systems these problems have been dealt with through using cables having substantially the same length or through lowering the clock frequency which however do not provide satisfactory solutions since it is desirable both to be able to use long cables and to have a clock frequency which is as high as possible to meet the demands of efficient, particularly high speed, systems.
What is needed is therefore an arrangement which receives redundant signals intended for a terminal or terminating unit as a user of the signal through which a high clock frequency can be applied and through which it is particularly possible to use long cables. Particularly an arrangement is needed through which it is possible to keep a number (n) of planes synchronized wherein n at least is two. Particularly an arrangement is needed through which the multiplication, e.g. particularly triplication protection principle of signals can be further taken advantage of without suffering from drawbacks such has having to lower the frequencies or apply too severe restrictions as to the length of cables etc.
A method is also needed through which protected signals can be transmitted to a terminating unit as a signal user allowing the signals to be transmitted at a high speed and wherein the length of the cables of the planes does not reduce the reliability.
Still further a telecommunications system is needed wherein protected (particularly high speed) signals can be transmitted to a terminating unit as user of the signal in a fast and reliable manner.
Therefore an arrangement as referred to above is provided which comprises a register arrangement in which is stored information relating to the initial delay between planes from the dynamic buffering means. Initial delay may e.g. be taken to mean the difference between read and write pointer for the static buffer of a plane after a reload operation, e.g. a first reload operation. Furthermore information is collected relating to the current delay of the first buffering means, i.e. the dynamic buffer after a (subsequent) reload operation in the first buffering means through which one plane is reloaded from another plane. The initial delay and the current delay, i.e. the difference between read and write pointers at a first occasion and at a subsequent occasion, e.g. the subsequent reload operation, are compared and via a control signal the next reload operation in the first buffering means is controlled so as to avoid end of buffer in the second buffering means, i.e. the static buffering means. If the dynamic buffer slips one clock cycle when it is restarted from another plane, e.g. a selected master plane, the static buffer for the reloaded plane will change its value in order to compensate for the change in the dynamic buffer and the current difference as referred to above is compared to the stored initial difference and a decision is taken as if to reload the dynamic buffer with an offset or not via said control signal the next time it is restarted. According to advantageous embodiments an offset can be used if the difference comprises one position or any other appropriate number of positions.
Particularly is in the register arrangement information stored relating to the position of the second buffering means at an initial start-up of the arrangement whereas the current position is given by the position of the second buffering means when a plane is reloaded from another plane in the first buffering means. Particularly the effect of the synchronization between planes in the first buffering means has on the second buffering means for a reload operation is established. The result is used to control the reloading in a subsequent reload operation. Particularly the first buffering means comprises a separate write pointer for each plane and a common read pointer which is common for all the planes.
The first buffering means moves data from a number of different clock systems, one of each plane, to a common clock system whereas the second buffering means aligns incoming data so that the frame alignment word from each of the planes is detected within one and the same clock cycle. Particularly a reload operation between planes in the first buffering means comprises copying of a write pointer of e.g. a selected master plane to a plane to be reloaded. If the delay changes, this is compensated for by the second buffering means. The copying operation may comprise copying the write pointer content of one plane to the write pointer of the plane to be reloaded with or without an offset depending on the control signal as referred to above.
Advantageously is in a register arrangement stored the initial difference between the read and write pointers of the second or static buffering arrangement of the synchronized signal and the current difference between the static inpointer and outpointer is detected when a reload operation has been done. If the current difference differs from the initial difference by a given value, e.g. a given number of positions, the dynamic write pointer of the reloaded plane is adjusted by an offset in the subsequent reload operation in the first buffering means. Particularly the difference between the initial difference or delay and the current difference or delay is a measure of the extent to which the write pointer of the second buffering means has slipped, i.e. if the number of available positions has decreased or increased in which case an adjustment is done towards the center of the buffer. Advantageously there are at least two redundant planes, i.e. at least duplication is applied. In an advantageous embodiment there are three planes which means that the signal is triplicated.
When the alignment word of a selected reference plane, e.g. a master plane, has been detected (the selection can be done in any appropriate manner), the conditions for calculating and storing the initial difference in the register arrangement are fulfilled. The register arrangement advantageously comprises an ordinary register.
An advantageous application of the invention is in the interface between a triplicated switch matrix or a cross-connect and a terminal access unit. Advantageously the write pointer in the first buffering means is reloaded using the control signal given by the delay change in the second buffering means. Advantageously the second buffering means compensates for delays introduced by the first buffering means and for static delays such as e.g. cable introduced delays etc.
Advantageously the control signal which as referred to above contains information about the previous difference and the current difference between the read and write pointers of the second buffering means and signals to logic circuit means in the first buffering means how to initiate the plane to be reloaded.
Particularly the first buffering means comprises one circular buffer for each plane.
Advantageously the second buffering means operates as a FIFO having a variable length.
Thus, in brief, the frame alignment word of a plane is detected. An external compensating loop advantageously provides for adjustment and the static buffer is set so that the frame alignment word of the master plane is in the middle of the static buffer. The other planes are adjusted so that the frame word is found within the same clock cycle when e.g. a plane is selected based on a majority selection.
In a particular embodiment means are provided for controlling the frequency of the common system clock to avoid collision between the read and write pointers of the first buffering means. Said controlling means may for example comprise a PLL (phase locked loop) with a voltage controlled oscillator (VCO).
The incoming clock systems may particularly comprise 20.48 MHz frequency clocks. For each incoming clock system there is advantageously one clock part module which modules implement the circular buffer functionality.
In a first embodiment the first and second buffering means respectively comprise separate buffering means, e.g. a dynamical buffer and a static, also denoted delay, buffer.
In an alternative embodiment the first and second buffering means comprise a common RAM.
The invention also provides a method for handling a number of protected incoming signals from a number of protection planes to a terminating unit, said method providing for handling of dynamic phase deviations between the planes and handling of static phase deviations between the planes. The first buffering means moves data from the signals of the different planes each having a clock system to a common system clock.
In second buffering means incoming data is aligned so that the frame alignment words from the different planes can be detected within the same clock cycle.
At e.g. an initial start-up of the arrangement, information is stored about the position of the read pointer in relation to the write pointer of the second buffering means after a reload operation when the signals have been synchronized into a common clock system.
When a subsequent reload operation from one plane to another is done in the first buffering means, the position of the read pointer in relation to the write pointer of the second buffering means is detected.
Then the initial position of the read pointer in relation to the write pointer is compared with the current position of the read pointer in relation to the write pointer.
If there is a difference between the initial value and the current value which exceeds a given value, e.g. if there is a difference, via a control signal the reloading of the plane is controlled the next time it is reloaded to prevent end of buffer in the second buffering means.
Advantageously a triplication protection method is used.
According to different embodiments the buffering means comprise separate buffering means formed by flip-flops or alternatively a common RAM is used forming the first and second buffering means.
A telecommunication system is also provided comprising an arrangement as disclosed above e.g. between a triplicated switch matrix and a terminal access unit.